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EN29F002 / EN29F002N
EN29F002 / EN29F002N 2 Megabit (256K x 8-bit) Flash Memory
FEATURES
* 5.0V 10% for both read/write operation * Read Access Time - 45ns, 55ns, 70ns, and 90ns * Fast Read Access Time - 70ns with Cload = 100pF - 45ns, 55ns with Cload = 30pF * Sector Architecture: One 16K byte Boot Sector, Two 8K byte Parameter Sectors, one 32K byte and three 64K byte main Sectors * Boot Block Top/Bottom Programming Architecture * High performance program/erase speed Byte program time: 10s typical Sector erase time: 500ms typical Chip erase time: 3.5s typical * JEDEC standard DATA polling and toggle bits feature * Hardware RESET Pin (n/a for EN29F002N) * Single Sector and Chip Erase * Sector Protection / Temporary Sector Unprotect (RESET = VID) * Sector Unprotect Mode * Embedded Erase and Program Algorithms * Erase Suspend / Resume modes: Read and program another sector during Erase Suspend Mode * 0.4 m double-metal double-poly triple-well CMOS Flash Technology * Low Vcc write inhibit < 3.2V * 100K endurance cycle * Package Options - 32-pin PDIP - 32-pin PLCC - 32-pin TSOP (Type 1) * Commercial and Industrial Temperature Ranges
* Low Standby Current - 1A CMOS standby current-typical - 1mA TTL standby current * Low Power Active Current - 30mA active read current - 30mA program / erase current * JEDEC Standard program and erase commands
GENERAL DESCRIPTION
The EN29F002 / EN29F002N is a 2-Megabit, electrically erasable, read/write non-volatile flash memory. Organized into 256K words with 8 bits per word, the 2M of memory is arranged in seven sectors (with top/bottom configuration), including one 16K Byte Boot Sector, two 8K Byte Parameter sectors, and four main sectors (one 32K Byte and three 64K Byte). Any byte can be programmed typically at 10s. The EN29F002 / EN29F002N features 5.0V voltage read and write operation. The access times are as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29F002 / EN29F002N has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E ) controls which eliminate bus contention issues. This device is designed to allow either single sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each sector.
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EN29F002 / EN29F002N
TABLE 1. PIN DESCRIPTION
Pin Name A0-A17 DQ0-DQ7 Function Addresses Data Input/Outputs Chip Enable Output Enable Write Enable Hardware Reset Sector Unprotect Supply Voltage (5V 10% ) Ground
CE OE WE RESET
NC on EN29F002N
FIGURE 1. LOGIC DIAGRAM
Vcc
18 A0 - A17 EN29F002T/B
8 DQ0 - DQ7
CE OE
WE
RESET
(n/a for EN29F002N)
Vcc Vss
Vss
TABLE 2. BLOCK ARCHITECTURE
TOP BOOT BLOCK
SECTOR
6 5 4 3 2 1 0
BOTTOM BOOT BLOCK
ADDRESSES
30000h - 3FFFFh 20000h - 2FFFFh 10000h - 1FFFFh 08000h - 0FFFFh 06000h - 07FFFh 04000h - 05FFFh 00000h - 03FFFh SIZE (Kbytes) 64 64 64 32 8 8 16
ADDRESSES
3C000h - 3FFFFh 3A000h - 3BFFFh 38000h - 39FFFh 30000h - 37FFFh 20000h - 2FFFFh 10000h - 1FFFFh 00000h - 0FFFFh
SIZE (Kbytes) 16 8 8 32 64 64 64
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EN29F002 / EN29F002N
BLOCK DIAGRAM
Vcc Vss RESET
N/A on EN29F002N
Block Protect Switches
DQ0-DQ7
Erase Voltage Generator State Control Program Voltage Generator Chip Enable Output Enable Logic
STB
Input/Output Buffers
WE
Command Register CE OE
Data Latch
Y-Decoder
STB
Y-Gating
Vcc Detector
Timer
Address Latch
X-Decoder
Cell Matrix
A0-A17
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EN29F002 / EN29F002N
FIGURE 2. PDIP
PDIP Top View
N/A for EN29F002N
VPP RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC PGM WE NC A17 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
FIGURE 3. TSOP
A17
WE N/A for EN29F002N RESET
EN29F002
FIGURE 4. PLCC
PLCC Top View
A12 A16 VCC A17 A12 A16 VCC A17 NC A15 RESET WE A15 VPP PGM
4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE DQ7
RESET is not applicable for EN29F002N
DQ2 DQ3 DQ5 DQ1 VSS DQ4 DQ6
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EN29F002 / EN29F002N
TABLE 3. OPERATING MODES 2M FLASH USER MODE TABLE
CE
USER MODE RESET
(n/a for EN29F002N)
WE
OE
RESET
A9
X X A9 A9 VID VID VID VID VID A9 X
A8
X X A8 A8 L/H L/H X X X A8 X
A6
X X A6 A6 L L L L H A6 X
A1
X X A1 A1 L L H X H A1 X
A0
X X A0 A0 L H L X L A0 X
Ax/y
X X Ax/y Ax/y X X X X X Ax/y X
DQ(0-7)
HI-Z HI-Z DQ(0-7) HI-Z MANUFACTURER ID DEVICE ID(T/B) CODE X X DIN(0-7) X
X H L L L L L L L L X
X X H H H H H L L L X
X X L H L L L VID VID H X
L H H H H H H H H H VID
STANDBY READ OUTPUT DISABLE READ MANUFACTURER ID READ DEVICE ID VERIFY SECTOR PROTECT ENABLE SECTOR PROTECT SECTOR UNPROTECT WRITE TEMPORARY SECTOR UNPROTECT
NOTES: 1) L = VIL, H = VIH, VID = 11.0V 0.5V 2) X = Don't care, either VIH or VIL
TABLE 4. DEVICE IDENTIFICTION 2M FLASH MANUFACTURER/DEVICE ID TABLE
A8 READ MANUFACTURER ID READ MANUFACTURER ID READ DEVICE ID (Top Architecture) READ DEVICE ID (Top Architecture) READ DEVICE ID (Bottom Architecture) READ DEVICE ID (Bottom Architecture) L H L H L H A6 L L L L L L A1 L L L L L L A0 L L H H H H DQ(7-0) HEX MANUFACTURER ID 7F MANUFACTURER ID 1C DEVICE ID 7F DEVICE ID 92 DEVICE ID 7F DEVICE ID 97
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EN29F002 / EN29F002N USER MODE DEFINITIONS
Reset Mode
EN29F002 features a Reset mode that resets the program and erase operation immediately to read mode. If reset (RESET = L) is executed when program or erase operation were in progress, the program or erase which was terminated should be repeated since data will be corrupted. This pin is not available for EN29F002N.
Standby Mode
The EN29F002 / EN29F002N has a CMOS-compatible standby mode which reduces the current to < 1A (typical). It is placed in CMOS-compatible standby when CE and the RESET pins are at VCC 0.5 V ( CE pin only, for EN29F002N). The device also has a TTL-compatible standby mode which reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when CE and RESET pins are at VIH. Another method of entering standby mode uses only the RESET pin (n/a for EN29F002N). When RESET pin is at VSS 0.3V, the device enters CMOS-compatible standby with current typically reduced to < 1 A. When RESET pin is at VIL, the device enters TTL-compatible standby with current reduced to < 1mA. When in standby modes, the outputs are in a highimpedance state independent of the OE input.
Read Mode
The EN29F002 / EN29F002N has two control functions which must be satisfied in order to obtain data at the outputs. Chip Enable ( CE ) is the power control and should be used for device selection. Output Enable ( OE ) is the output control and should be used to gate data to the output pins, provided the device is selected. Read is selected when both CE and OE pins are held at VIL with the W E pin held at VIH. Address access time (tACC) is equal to the delay from stable addresses to valid output data. Assuming that addresses are stable, chip enable access time (tCE) is equal to the delay from stable CE to valid data at output pins. Data is available at the outputs after output enable access time (tOE) from the falling edge of OE , assuming the CE has been LOW and addresses have been stable for at least tACC - tOE.
Output Disable Mode
When the CE or OE pin is at a logic high level (VIH), the output from the EN29F002 / EN29F002N is disabled. The output pins are placed in a high impedance state.
Auto Select Identification Mode
The manufacturer and device type can be identified by hardware or software operations. This mode allows applications or programming equipment automatically matching the device with its corresponding interface characteristics. To activate the Auto Select Identification mode, the programming equipment must force 12.0 V 0.5V on address line A9 of the EN29F002T/B. Two identifier bytes can then be sequenced from the device outputs by toggling address lines A0 and A8 from VIL to VIH. The manufacturer and device identification may also be read via the command register. By following the command sequence referenced in the Command Definition Table (Table 5). This method is desirable for in-system identification (using only + 5.0V). When A0 = A1 = A6 = VIL and by toggling A8 from VIL to VIH, the Manufacturer ID can be read as Eon = 7F, 1C (hex) to identify EON . When A0 = VIH, A1 = A6 = VIL, and by toggling A8 from VIL to VIH, the
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EN29F002 / EN29F002N
Device Code can be read as 7F, 92 (hex) for EN29F002T or as 7F, 97 (hex) for EN29F002B (See Table 4). All identifiers for manufacturer and device codes possess odd parity with the DQ7 defined as the parity bit.
Write Mode
Write is used for device programming and erase through the command register. This mode is selected with CE = W E = L and OE = H. The contents of the command register are the inputs to the internal state machine. The command register is a set of latches used to store the commands along with the addresses and data information needed to execute that command. Address latching occurs on the falling edge of W E or CE (whichever occurs later) and data latching occurs on the rising edge of W E or CE (whichever occurs first).
Temporary Sector Unprotect Mode
EN29F002 allows protected sectors to be temporarily unprotected for making changes to data stored in a protected sector in system (n/a for EN29F002N). To activate the temporary sector unprotect, the RESET pin must be set to a high voltage of VID (11V). In this mode, protected sectors can be programmed or erased by selecting the sector addresses. Once the high voltage, VID, is removed from RESET pin, all previously protected sectors will revert to their protected state.
RESET Hardware Reset Mode (not available on EN29F002N)
Resetting the EN29F002 device is performed when the RESET pin is set to VIL and kept low for at least 500ns. The internal state machine will be reset to the read mode. Any program/erase operation in progress during hardware reset will be terminated and data may be corrupted. If the RESET pin is tied to the system reset command, the device will be automatically reset to the read mode and enable the system's microprocessor to read the boot-up firmware from the FLASH memory.
COMMAND DEFINITIONS
The operations of the EN29F002 are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to the read mode.
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EN29F002 / EN29F002N
Table 5. EN29F002 Command Definitions
Write Cycles Req'd
1
st
2
nd
3
rd
4
th
5
th
6
th
Command Sequence Read/Reset Read/Reset Read/Reset AutoSelect Manufacturer ID AutoSelect Device ID
(Top Boot)
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
1 4 4 4 4 4 4 6 6 1 1
XXXh 555h 555h 555h 555h 555h 555h 555h 555h xxxh xxxh
F0h RA AAh AAAh AAh AAAh AAh AAAh AAh AAAh AAh AAAh AAh AAAh AAh AAAh AAh AAAh B0h 30h
RD 55h 55h 55h 55h 55h 55h 55h 55h
555h 555h 555h 555h 555h 555h 555h 555h
F0h 90h 90h 90h 90h A0h 80h 80h
AutoSelect Device ID
(Bottom Boot)
AutoSelect Sector Protect Verify Byte Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Notes:
RA 000h/ 100h 001h/ 101h 001h/ 101h SA & 02h PA 555h 555h
RD 7Fh/ 1Ch 7Fh/ 92h 7Fh/ 97h 00h/ 01h PD AAh AAAh AAh AAAh
55h 55h
555h SA
10h 30h
RA = Read Address: address of the memory location to be read. This one is a read cycle. RD = Read Data: data read from location RA during Read operation. This one is a read cycle. PA = Program Address: address of the memory location to be programmed PD = Program Data: data to be programmed at location PA SA = Sector Address: address of the sector to be erased. Address bits A17-A13 uniquely select any sector.
Byte Programming Command
Programming the EN29F002 is performed on a byte-by-byte basis using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. The program operation is terminated automatically by an internal timer. Address is latched on the falling edge of CE or W E , whichever is last; data is latched on the rising edge of CE or W E , whichever is first. The program operation is completed when EN29F002 returns the equivalent data to the programmed location. Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is exceeded, DQ5 will produce a logical "1" and a Reset command can return the device to Read mode. EN29F002 ignores commands written during Byte Programming. If a hardware RESET occurs during Byte Programming, data at the programmed location may get corrupted. Programming is allowed in any sequence and across any sector boundary.
Chip Erase Command
An auto Chip Erase algorithm is employed when the Chip Erase command sequence is performed. Although the Chip Erase command requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles and the chip erase command, the user does not need to do anything else after that, except check to see if the operation has completed. The Auto Chip Erase algorithm automatically programs and verifies the entire memory array for an all "0" pattern prior to
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EN29F002 / EN29F002N
the erase. Then the EN29F002 will automatically time the erase pulse width, verify the erase, return the sequence count, provide a erase status through DATA POLLING (data on DQ7 is "0" during the operation and "1" when completed, provided the status is not read from a protected sector), and returns to the READ mode after completion of Chip Erase.
Sector Erase Command
Sector Erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and the Sector Erase command. Any sector may be erased by latching any address within the desired sector on the falling edge of W E while the Erase Command (30H) is latched on the rising edge of W E . This device does not support multiple sector erase commands. Sector Erase operation will commence immediately after the first 30h command is written. The first sector erase operation must finish before another sector erase command can be given. The EN29F002 device automatically programs and verifies all memory locations in the selected sector for an all "0" pattern prior to the erase. Unselected sectors are unaffected by the Sector Erase command. The EN29F002 requires no timing signals during sector erase. Erase is completed when data on DQ7 becomes "1", and the device returns to the READ mode after completion of Sector Erase.
Erase Suspend / Resume Command
Erase suspend allows interruption of sector erase operations to perform data reads from sector not being erased. Erase suspend applies only to Sector Erase operations. EN29F002 ignores any commands during erase suspend other than the assertion of the RESET pin (n/a for EN29F002N) or Erase Resume commands. Writing erase resume continues erase operations. Addresses are DON'T CARE when writing Erase Suspend or Erase Resume commands. EN29F002 takes 0.1 - 15 s to suspend erase operations after receiving Erase Suspend command. Check completion of erase suspend by polling DQ7 and/or DQ6. EN29F002 ignores redundant writes of erase suspend command. EN29F0002 defaults to erase-suspend-read mode while an erase operation has been suspended. While in erase-suspend-read mode, EN29F002 allows reading data in any sector not undergoing sector erase, which is treated as standard read mode. Write the Resume command 30h to continue operation of Sector erase. EN29F002 ignores redundant writes of the Resume command. EN29F002 permits multiple suspend/resume operations during sector erase.
Sector Protect and Unprotect
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operation in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Contact Eon Silicon Devices, Inc. for an additional supplement on this feature.
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EN29F002 / EN29F002N WRITE OPERATION STATUS
DQ7 DATA Polling
The EN29F002 provides DATA Polling on DQ7 to indicate to the host system the status of the embedded operations. The DATA Polling feature is active during the Byte Programming, Sector Erase, Chip Erase, Erase Suspend. (See Table 6) When the Byte Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the Byte Programming, an attempt to read the device will produce the true data last written to DQ7. For the Byte Programming, DATA polling is valid after the rising edge of the fourth WE or C E pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7 output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last rising edge of the sector erase W E or C E pulse.
DATA Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the address used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable ( OE ) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts. The flowchart for DATA Polling (DQ7) is shown on Flowchart 5. The DATA Polling (DQ7) timing diagram is shown in Figure 8.
DQ6 Toggle Bit I
The EN29F002 provides a "Toggle Bit" on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by toggling OE or CE ) will result in DQ6 toggling between "zero" and "one". Once the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the last rising edge of the Sector Erase Command (30h) W E pulse. In Byte Programming, if the sector being written to is protected, DQ6 will toggle for about 2s, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 s. The chip will then return to the read mode without changing data in all protected sectors. Toggling either CE or OE will cause DQ6 to toggle.
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EN29F002 / EN29F002N
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9.
DQ5 Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". (The Toggle Bit (DQ6) should also be checked at this time to make sure that the DQ5 is not a "1" due to the device having returned to read mode.) This is a failure condition which indicates that the program or erase cycle was not successfully completed. DATA Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still function under this condition. Setting the CE to VIH will partially power down the device under those conditions. The O E and W E pins will control the output disable functions as described in Table 3. The DQ5 failure condition will also appear if the user tries to program a "1" to a location that was previously programmed to a "0". In this case, the device goes into Hang or Error mode out and never completes the Embedded Program Algorithm. Hence, the system never reads valid data on DQ7 and DQ6 never stops toggling. Once the device exceeds the timing limits, DQ5 will indicate a "1". Please note that this is not a device failure condition since the device was used incorrectly. If timing limits are exceeded, reset the device. (See Table 6)
DQ3 Sector Erase Command Timeout
This device does not support multiple sector erase commands. DQ3 will go high immediately after the first 30h command (the sixth write cycle). Any extra 30h commands will be ignored (or taken as a resume command if erase suspended).
DQ2 Erase Toggle Bit II
In the sector erase operation, DQ2 will toggle with OE or CE when a read is attempted within the sector that is being erased. DQ2 will not toggle if the read address is not within the sector that is selected to be erased. In the chip erase operation, however, DQ2 will toggle with OE or CE regardless of the address given by the user. This is because all sectors are to be erased. (See Table 6)
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EN29F002 / EN29F002N
Table 6. Status Register Bits
DQ Name Logic Level `1' `0' 7 Definition Erase Complete or erase sector in Erase suspend Erase On-Going Program Complete or data of non-erase sector during Erase Suspend Program On-Going Erase or Program On-going Read during Erase Suspend Erase Complete Program or Erase Error Program or Erase On-going Erase operation start Erase timeout period on-going Chip Erase, Erase or Erase suspend on currently addressed sector. (When DQ5=1, Erase Error due to currently addressed sector. Program during Erase Suspend ongoing at current address
DATA
POLLING
DQ7
DQ7 `-1-0-1-0-1-0-1-' DQ6 6 5 TOGGLE BIT ERROR BIT ERASE TIME BIT `-1-1-1-1-1-1-1-` `1' `0' `1' `0'
3
`-1-0-1-0-1-0-1-'
2
TOGGLE BIT DQ2 Erase Suspend read on non Erase Suspend Sector
Notes: DQ7 DATA Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits
DQ5 for Program or Erase Success. DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5 Error Bit: set to "1' if failure in programming or erase DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES). DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased sector.
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EN29F002 / EN29F002N DATA PROTECTION
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE = VIL, W E = VIL and OE = VIH, the device will not accept commands on the rising edge of WE.
Low VCC Write Inhibit
During VCC power-up or power-down, the EN20F002 locks out write cycles to protect against any unintentional writes. If VCC < VLKO, the command register is disabled and all internal program or erase circuits are disabled. Under this condition, the device will reset to the READ mode. Subsequent writes will be ignored until VCC > VLKO.
Write "Noise" Pulse Protection
Noise pulses less than 5ns on OE , CE or WE will neither initiate a write cycle nor change the command register.
Logical Inhibit
If CE =VIH or WE=VIH, writing is inhibited. To initiate a write cycle, CE and W E must be a logical "zero". If CE , W E , and OE are all logical zero (not recommended usage), it will be considered a write.
Sector Protection/Unprotection
When the device is shipped, all sectors are unprotected. Each sector can be separately protected against data changes. Using hardware protection circuitry enabled at user's site with external programming equipment, both program and erase operations may be disabled for any specified sector or combination of sectors. Verification of write protection for a specific sector can be achieved with an Auto Select ID read command at location 02h where the address bits A17 - A13 select the defined sector (see Table 5). A logical "1" at DQ0 means a protected sector and a logical "0" means an unprotected sector. The Sector Unprotect disables sector protection in all sectors in one operation to implement code changes. All sectors must be placed in protection mode using the protection algorithm mentioned above before unprotection can be executed. Additional details on this feature are provided in a supplement, which can be obtained by contacting a representative of Eon Silicon Devices, Inc.
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EN29F002 / EN29F002N EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program Command Sequence (shown below)
Data Poll Device
Increment Address
No
Last Address?
Yes Programming Done
Flowchart 2. Embedded Program Command Sequence
See the Command Definitions section for more information.
5555H / AAH
2AAAH / 55H
5555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
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EN29F002 / EN29F002N
Flowchart 3. Embedded Erase
START
Write Erase Command Sequence (shown below)
Data Polling Device or Toggle Bit Successfully Completed
ERASE Done
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EN29F002 / EN29F002N
Flowchart 4. Embedded Erase Command Sequence
See the Command Definitions section for more information.
Chip Erase
Sector Erase
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
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Flowchart 5. DATA Polling Algorithm
Start
Read Data
DQ7 = Data? No No DQ5 = 1? Yes Read Data
Yes
DQ7 = Data? No Fail
Yes
Pass
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EN29F002 / EN29F002N
Flowchart 6. Toggle Bit Algorithm
Start
Read Data
DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Data
No
DQ6 = Toggle? Yes Fail
No
Pass
4800 Great America Parkway, Suite 202 18 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N
Flowchart 7. Temporary Sector Unprotect Algorithm (Not available for EN29F002N)
Start
RESET = VID
(Note 1)
Perform Erase or Program Operations
RESET = VIH
Temporary Block Unprotect Done
(Note 2)
Notes: 1. All protected sectors unprotected. 2. All previous protected sectors are protected once again.
4800 Great America Parkway, Suite 202 19 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +125C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . . . . -0.5 V to 7.0 V A9, OE# (Note 2) . . . . . . . . . . . . . . . -0.5 V to 11.5 V All other pins (Note 1) . . . . . . . . . . . . -0.5 V to Vcc+0.5V Output Short Circuit Current (Note 3) . . . . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot VSS to -1.0V for periods of up to 50 ns and to -2.0 V for periods of up to 20 ns. See Left Figure below. Maximum DC voltage on input and I/O pins is V CC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Right Figure below. Minimum DC input voltage on A9 pin is -0.5 V. During voltage transitions, A9 and OE# may undershoot VSS to -1.0V for periods of up to 50 ns and to -2.0 V for periods of up to 20 ns. See Left Figure. Maximum DC input voltage on A9 and OE# is 11.5 V which may overshoot to 12.5 V for periods up to 20 ns. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
2.
3.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (T A ) . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (T A ). . . . . . . . . . -40C to +85C VCC Supply Voltages VCC for 5% devices . . . . . . . . . . . . +4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . . . +4.50 V to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed.
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
4800 Great America Parkway, Suite 202 20 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N
Table 7. DC Characteristics (Ta = 0C to 70C or - 40C to 85C; VCC = 5.0V 10%)
Symbol ILI ILO ICC1 ICC2 ICC3
(2) ICC4
Parameter Input Leakage Current Output Leakage Current Supply Current (read) TTL Byte Supply Current (Standby) TTL Supply Current (Standby) CMOS
(1)
Test Conditions 0V VIN Vcc 0V VOUT Vcc CE# = VIL; OE# = VIH; f = 6MHz CE# = VIH RESET# = CE# = Vcc 0.2V Byte program, Sector or Chip Erase in progress
Min
Max 5 5 30 1.0 5.0 30
Uni t A A mA mA A mA V V V V V
Supply Current (Program or Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS
VIL VIH VOL VOH VID ILIT VLKO
-0.5 2 IOL = 2 mA IOH = -2.5 mA IOH = -100 A 2.4 Vcc - 0.4V 10.5
0.8 Vcc 0.5 0.45
A9 Voltage (Electronic Signature) and RESET# Voltage (Temporary Sector Unprotect) A9 and RESET# Current (Electronic Signature) Supply voltage (Erase and Program lock-out)
11.5
V
A9, RESET# = VID 3.2
100 4.2
A V
Notes:
(1) RESET# pin input buffer is always enabled so that it draws power if not at full CMOS supply voltages
4800 Great America Parkway, Suite 202 21 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
Table 8. AC CHARACTERISTICS Read-only Operations Characteristics
Parameter Symbols JEDEC Standard Description Read Cycle Time Address to Output Delay Chip Enable To Output Delay Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time from Addresses, CE or OE , whichever occurs first Test Setup Min Speed Options -45 45 45 45 25 10 10 0 -55 55 55 55 30 15 15 0 -70 70 70 70 30 20 20 0 -90 90 90 90 35 20 20 0 Unit ns ns ns ns ns ns ns
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX
tRC tACC tCE tOE tDF tDF tOH tReady
CE = VIL OE = VIL
Max Max Max Max Max Min
OE = VIL
Max
RESET Pin Low to Read
Mode (n/a for EN29F002N)
20
20
20
20
s
Notes: For -45,-55
Vcc = 5.0V 5% Output Load : 1 TTL gate and 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to 3.0 V Timing Measurement Reference Level, Input and Output: 1.5 V Vcc = 5.0V 10% Output Load: 1 TTL gate and 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V
For all others:
4800 Great America Parkway, Suite 202 22 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
Table 9. AC CHARACTERISTICS Write (Erase/Program) Operations
Parameter Symbols JEDEC Standard Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and DATA Polling Min Min Min Min Min Min MIn Min Min -45 45 0 35 20 0 0 0 10 0 Speed Options -55 55 0 45 25 0 0 0 10 0 -70 70 0 45 30 0 0 0 10 0 -90 90 0 45 45 0 0 0 10 0 Unit ns ns ns ns ns ns ns ns ns
tAVAV tAVWL tWLAX tDVWH tWHDX
tWC tAS tAH tDS tDH tOES tOEH
tGHWL tELWL tWHEH tWLWH tWHDL
tGHWL tCS tCH tWP tWPH
Read Recovery Time before Write ( OE High to W E Low)
CE SetupTime
CE Hold Time
Write Pulse Width Write Pulse Width High Programming Operation
Min Min Min Min Typ Max
0 0 25 20 7 200 0.3 5 3 35 50 500 500
0 0 30 20 7 200 0.3 5 3 35 50 500 500
0 0 35 20 7 200 0.3 5 3 35 50 500 500
0 0 45 20 7 200 0.3 5 3 35 50 500 500
ns ns ns ns s s s s s s s ns ns
tWHWH1 tWHWH1 tWHWH2 tWHWH2 tWHWH3 tWHWH3 tVCS tVIDR tRP tRSP
Sector Erase Operation
Typ Max
Chip Erase Operation
Typ Max
Vcc Setup Time Rise Time to VID
Min Min
RESET Pulse Width (n/a for EN29F002N)
Min
Min
RESET Setup Time
(n/a for EN29F002N)
4
4
4
4
s
4800 Great America Parkway, Suite 202 23 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
Table 10. AC CHARACTERISTICS Write (Erase/Program) Operations Alternate CE Controlled Writes
Parameter Symbols JEDEC Standard Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Min Min Min Min Min Min 0 10 Min Min Min Min Min Typ Max -45 45 0 35 20 0 0 0 10 0 0 0 25 20 7 200 0.3 5 3 35 50 500 500 Speed Options -55 55 0 45 25 0 0 0 10 0 0 0 30 20 7 200 0.3 5 3 35 50 500 500 -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 200 0.3 5 3 35 50 500 500 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 200 0.3 5 3 35 50 500 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s ns ns
tAVAV tAVEL tELAX tDVEH tEHDX
tWC tAS tAH tDS tDH tOES tOEH
tGHEL tWLEL tEHWH tELEH tEHEL
tGHEL tWS tWH tCP tCPH
Toggle and Data Polling Read Recovery Time before Write ( OE High to CE Low)
W E SetupTime W E Hold Time
Write Pulse Width Write Pulse Width High Programming Operation
tWHWH1 tWHWH1 tWHWH2 tWHWH2 tWHWH3 tWHWH3 tVCS tVIDR tRP tRSP
Sector Erase Operation
Typ Max
Chip Erase Operation
Typ Max
Vcc Setup Time Rise Time to VID
Min Min Min
Pulse Width (n/a for EN29F002N) Min
RESET
RESET Setup Time
(n/a for EN29F002N)
4
4
4
4
s
4800 Great America Parkway, Suite 202 24 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
Table 11. ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Endurance Typ 0.3 3 7 2 100K Limits Max 5 35 200 5 Unit sec sec s sec cycles Minimum 100K cycles guaranteed Comments Excludes 00H programming prior to erasure Excludes system level overhead
Table 12. LATCH UP CHARACTERISTICS
Parameter Description Input voltage with respect to Vss on A9 and OE , and RESET Input voltage with respect to Vss on all other pins Vcc Current Min -1.0 V -1.0 V -100 mA Max 12.0 V Vcc + 1.0 V 100 mA
Note : These are latch up characteristics and the device should never be put under these conditions. Refer to Absolute Maximum ratings for the actual operating limits.
Table 13. 32-PIN PLCC PIN CAPACITANCE @ 25C, 1.0MHz
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 4 8 8 Max 6 12 12 Unit pF pF pF
Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25C, 1.0MHz
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
4800 Great America Parkway, Suite 202 25 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
Table 15. DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years
4800 Great America Parkway, Suite 202 26 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
SWITCHING WAVEFORMS
Figure 5. AC Waveforms for READ Operations
Figure 6. AC Waveforms for Chip/Sector Erase Operations
Notes:
1. SA is the sector address for sector erase.
4800 Great America Parkway, Suite 202 27 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
SWITCHING WAVEFORMS (continued)
Figure 7. Program Operation Timings
Notes: 1. 2. 3. 4. 5. PA is address of the memory location to be programmed. PD is data to be programmed at byte address. /DQ7 is the output of the complement of the data written to the device. DOUT is the output of data written to the device. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm Operations
Notes:
*DQ7 = Valid Data (The device has completed the embedded operation).
4800 Great America Parkway, Suite 202 28 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
Notes: *DQ6 stops toggling (The device has completed the embedded operation).
Figure 10. Temporary Sector Unprotect Timing Diagram
4800 Great America Parkway, Suite 202 29 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
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EN29F002 / EN29F002N
SWITCHING WAVEFORMS (continued)
Figure 11. /RESET Timing Diagram
Figure 12. Alternate /CE Controlled Write Operation Timings
Notes: 1. 2. 3. 4. 5. PA is address of the memory location to be programmed. PD is data to be programmed at byte address. /DQ7 is the output of the complement of the data written to the device. DOUT is the output of data written to the device. Figure indicates last two bus cycles of four bus cycle sequence.
4800 Great America Parkway, Suite 202 30 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N
ORDERING INFORMATION
EN29F002 T
- 45
P
I TEMPERATURE RANGE (Blank) = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE P = 32 Plastic DIP J = 32 Plastic PLCC T = 32 Plastic TSOP SPEED 45 = 45ns 55 = 55ns 70 = 70ns 90 = 90ns
BOOT BLOCK ARCHITECTURE T = Top Block B = Bottom Block
BASE PART NUMBER EN = EON Silicon Devices 29F = FLASH, 5V 002 = 256K x 8 (Blank) = with RESET function N = without RESET function
4800 Great America Parkway, Suite 202 31 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685
EN29F002 / EN29F002N Revisions List
A: Preliminary B (2001.07.03): Table 7. Icc3 is with RESET# pin at full CMOS levels Pg. 13 Logical Inhibit section now says that if CE , W E , and OE are all logical zero (not recommended usage), it will be considered a write. VID is everywhere changed to be VID =11.5 0.5V C (2001.07.05): VID is everywhere changed to be VID =11.0 0.5V "block" changed to "sector" everywhere appropriate. Deleted Sector Un/Protect flow charts (we have a supplement for that) RESET# = VID and not VPP on first page. LACTHUP >= 200mA line removed from first page Chip erase and Sector Erase command descriptions modified. DQ7,DQ5,DQ3 status polling descriptions modified. Table 7 and Table 12 modified Absolute Maximum Ratings section added
4800 Great America Parkway, Suite 202 32 Santa Clara, CA 95054 Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680 Fax: 408-235-8685

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